The present invention relates to a semiconductor circuit having p- and n-channel MOS transistors.
A semiconductor device of the so-called silicon-on-sapphire (SOS) structure is known which has semiconductor elements formed on an insulating substrate so as to improve the integration density of the MOS integrated circuit and to improve circuit characteristics. An SOS semiconductor device thus uses an insulating substrate. Therefore, as compared with a semiconductor device using a general semiconductor substrate, the stray capacitance is smaller and the frequency characteristics are improved. Furthermore, since the elements can be easily insulated with smaller isolation spaces, high integration may be easily attained.
FIGS. 1 and 2 are respectively a circuit diagram of a CMOS inverter and a schematic plan view of an SOS semiconductor device constituting this CMOS inverter. This CMOS inverter has p- and n-channel MOS transistors TP1 and TN1 of depletion-type (D-type), the gates of which are coupled to an input terminal VI, the drains of which are respectively connected to a positive power source terminal VD and a ground terminal VS, and the sources of which are connected to an output terminal VO. These MOS transistors TP1 and TN1 include as shown in FIG. 2, p- and n-type semiconductor layers 10P and 10N formed on a sapphire substrate 12, and a gate electrode layer 14 formed crosswise over the semiconductor layers 10P and 10N as insulated therefrom. Adjacent first ends of the semiconductor layers 10P and 10N are both connected to an interconnection layer 16 for the output line. The other end of the p-type semiconductor layer 10P is connected to an interconnection layer 18 for the positive power source line. The other end of the n-type semiconductor layer 10N is connected to an interconnection layer 20 for the ground line. Of course, in this case a sufficiently thick insulation layer (not shown) is formed between overlapped portions of the interconnection layer 18 and the n-type layer 10N, and no active transistor is formed in a corresponding area (which is hatched in FIG. 2).
As shown in FIG. 2, in order to electrically insulate the p- and n-type layers 10P and 10N from each other, they need only be formed with a small gap therebetween. Therefore, the occupying area of the CMOS inverter may be made very small.
FIGS. 3 and 4 are respectively a circuit diagram of a CMOS NOR gate circuit and a schematic plan view of an SOS semiconductor device constituting the CMOS NOR gate. The CMOS NOR gate circuit has D-type p-channel MOS transistors TP2 and TP3 whose current paths are serially connected between the power source terminal VD and the output terminal, and D-type n-channel MOS transistors TN2 and TN3 whose current paths are each connected between the output terminal VO and the power source terminal VS. As shown in FIG. 4, the p-channel MOS transistors TP2 and TP3 includes a p-type semiconductor layer 30 formed on a sapphire substrate 32, and gate electrode layers 34 and 36 which are formed crosswise over the p-type semiconductor layer 30 as insulated therefrom. Similarly, the n-channel MOS transistor TN2 includes an n-type semiconductor layer 38 formed on the sapphire substrate 32, and the gate electrode layer 34. The n-channel MOS transistor TN3 includes an n-type semiconductor layer 40 formed on the sapphire substrate 32 and the gate electrode layer 36. An insulating layer (not shown) between the gate electrode layer 34 and the n-type semiconductor layer 40 and an insulating layer (not shown) between the gate electrode layer 36 and the n-type semiconductor layer 38 are formed sufficiently thick. The transistors are not formed at the crossing regions (hatched parts) of these layers.
One end of each of the p- and n-type semiconductor layers 30, 38 and 40 are connected to an interconnection layer 42 for the output line. The other end of the p-type semiconductor layer 30 is connected to an interconnection layer 44 for the positive power source line. The other ends of the n-type semiconductor layers 38 and 40 are both connected to an interconnection layer 46 for the ground line.
In the NOR gate circuit device shown in FIG. 4, if the p- and n-type semiconductor layers 30, 38 and 40 are formed with slight distances therebetween, they may be electrically insulated from each other. Therefore, the occupying area of the NOR gate circuit device may be reduced.
However, in the semiconductor circuit shown in FIGS. 1 and 3, the p-channel MOS transistor is connected to the positive power source terminal VD which is set at a high potential, and the n-channel MOS transistor is connected to the ground terminal VS which is set at a low potential. Therefore, if the p- and n-type semiconductor layers for these p- and n-channel MOS transistors are formed in contact with each other, the operating voltage of the circuit is limited. More specifically, when the p- and n-type semiconductor layers are formed in contact with each other, if an operating voltage higher than the forward contact potential difference at the pn junction is applied between the positive power source terminal VD and the ground terminal VS, a forward current flows through, the pn junction. For this reason, the operating voltage must be set to be lower than the forward contact potential difference at the pn junction.